1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly but not by way of limitation, to a layout structure of semiconductor memory device having an input/output sense amplifier.
2. Description of Related Art
Semiconductor memory devices widely used in computers and communication products etc. are based on a hierarchy of local input/output lines (LIO) and global input/output lines (GIO). FIG. 1 illustrates a layout of semiconductor memory device having such a hierarchical structure according to a conventional art.
Referring to FIG. 1, a conventional semiconductor memory device 100 layout includes a plurality of memory banks A, B, C, D, E, F, G and H and a corresponding plurality of column decoders 110, row decoders 130, column control and fuse circuits 112, and row control circuits 132.
A column decoder 110 associated with each memory bank is positioned near one side of each memory bank, and a row decoder 130 is positioned near another side of each memory bank. A column control and fuse circuit 112 for a redundancy and control of the column decoder is positioned adjacent to each column decoder 110, and a row control circuit 132 for a control of the row decoder 130 is positioned adjacent to each row decoder 130.
Peripheral circuit area 170 includes multiple input/output sense amplifier (IOSA) areas. For example input/output sense amplifier area 150 is disposed in the peripheral circuit area 170 between memory bank A and memory bank E. The input/output sense amplifier area 150 includes multiple input/output sense amplifiers (not shown). Each of the input/output sense amplifiers in input/output sense amplifier area 150 are connected to a global input/output line GIO of the memory bank A and a global input/output line GIO of the memory bank E. That is, the memory bank A and the memory bank E share the input/output sense amplifiers included in input/output sense amplifier area 150.
The layout structure of semiconductor memory device as described above is generally well known in the art, thus further detail will be omitted.
FIG. 2 illustrates a data read path in a semiconductor memory device according to a conventional art. As illustrated in FIG. 2, a word line of selected memory cell MC is enabled and so data is developed into a bit line BL. A bit line sense amplifier BLSA senses and amplifies the data. The data output from the bit line sense amplifier BLSA is transferred through a local input/output line LIO to a multiplexer IOMUX. The data is transferred through the global input/output line GIO to the input/output sense amplifier IOSA. The input/output sense amplifier IOSA senses and amplifies the data, converts it into a CMOS level, and transmits it through a first data line FDIO. The data transmitted through the first data line FDIO is converted into serial data through a parallel to serial transformer (RDORDER) and then is transmitted to the data pad DQ and output from the memory device. In some conventional applications, a data output buffer (not shown) may be used prior to transmitting the data to the data pad DQ.
There is a need for highly-integrated semiconductor memory devices with faster data transfer speeds.